Devansh Patel ASIC Design Engineer
Santa Clara, CA • asiceng@gmail.com • +1 408-555-0192
Profile Summary
- ASIC Design Engineer with 9 years of experience designing GPU and AI accelerator ASICs across datacenter AI, gaming GPUs, and networking silicon, specializing in RTL microarchitecture, low-power design, and timing closure on advanced-node SoCs.
- Solid technical background across HDL (SystemVerilog, Verilog), verification on UVM, synthesis (Synopsys Design Compiler, Cadence Genus), STA on Synopsys PrimeTime, CDC on Synopsys Spyglass CDC, on-chip buses (AXI4, AHB-Lite), and tapeout on TSMC N5, with strong fundamentals in constraint-driven RTL, coverage-driven verification, and disciplined PPA convergence on every tapeout.
- Deep expertise in RTL design and microarchitecture, functional verification and coverage closure, synthesis, STA, and timing closure across PVT corners, and low-power design and UPF flows on advanced nodes, applying practices such as UVM and SystemVerilog assertions and CDC and reset-domain analysis to deliver PPA-optimal, verifiable, and silicon-clean ASIC IPs.
- Engaged collaborator working cross-functionally with DV, DFT, Physical Design, and Architecture leadership in tape-out-paced silicon programs, contributing to RTL + verification-plan reviews, timing / power sign-off war rooms, and post-silicon retrospectives with a pragmatic, ownership-first mindset.
- Senior engineer who shares technical excellence and fosters a culture of design-review rigor and written verification-plan discipline through code-review coaching and verification-plan mentorship, while running ASIC design-review board sessions and authoring widely adopted RTL-style and UVM-pattern handbooks.
Technical Skills
- HDL & RTL:
- SystemVerilog, Verilog-2001, VHDL (legacy), SystemC (TLM), SystemVerilog assertions (SVA), parameterized RTL
- Verification:
- UVM, SystemVerilog assertions, constrained-random stimulus, functional + code coverage, formal verification (JasperGold, OneSpin), VCS / Xcelium / Questa
- Synthesis & Logic Impl.:
- Synopsys Design Compiler, Cadence Genus, Fusion Compiler, SDC authoring, lint-clean RTL (Spyglass Lint), area / frequency / power trade-offs
- STA & Timing:
- Synopsys PrimeTime, Cadence Tempus, setup / hold sign-off, MCMM / OCV, multi-corner / multi-mode analysis, ECO timing fixes
- Low Power Design:
- UPF (IEEE 1801), clock gating, power gating, multi-Vt cells, DVFS, retention flops, isolation / level shifters, low-power verification
- CDC, Reset & Integration:
- Spyglass CDC + RDC, Cadence Conformal, async FIFOs, 2-FF synchronizers, gray-code crossings, reset trees, IP integration
- DFT (Design for Test):
- Scan insertion, MBIST, boundary scan / JTAG (IEEE 1149.1), test compression, ATPG (TetraMAX), fault coverage, silicon debug
- Physical Design Awareness:
- Floorplan-aware RTL, ICC2 / Innovus collaboration, parasitics (RC extraction), SI / PI awareness, post-route ECO, sign-off hand-off
Education
UC San Diego
M.S. in Electrical and Computer Engineering
Work Experience
NVIDIA
Senior ASIC Design Engineer
- Own RTL design and microarchitecture for NVIDIA's next-gen AI accelerator GPU across 3 IP blocks and 5 RTL releases, coordinating compute-pipeline microarchitecture, memory subsystem and arbiter, and tensor-engine integration with influence across 30+ engineers across 4 teams.
- Built UVM with SystemVerilog assertions testbenches with 180+ UVM sequences and constrained-random scenarios, hitting 99.6% functional coverage at sign-off across the IP releases.
- Ran synthesis and logic implementation in Synopsys Design Compiler with disciplined SDC constraints at 1.4 GHz pipeline clock, and shipped lint-clean RTL hitting 12% smaller area than baseline RTL.
- Closed STA sign-off in Synopsys PrimeTime across setup, hold, and OCV margins, taking WNS from -180 ps to +18 ps and shipping timing clean across all 36 PVT corners.
- Drove low-power design with UPF-based power intent, applying clock gating, multi-Vt cells, and DVFS across the compute pipeline, hitting 22% lower dynamic power vs. baseline.
- Designed the clocking and reset architecture across 8 asynchronous clock domains with async FIFOs and 2-FF synchronizers, running Synopsys Spyglass CDC + RDC to zero CDC violations at sign-off.
- Partnered with DFT on scan insertion, MBIST, and on-chip compression, hitting 99.2% stuck-at + 95% transition coverage via ATPG and qualifying first-silicon scan pass on every IP.
Marvell Technology
ASIC Design Engineer
- Partnered with Physical Design on the 5G baseband SoC on TSMC N7, handing off floorplan-aware RTL, parasitics-aware constraints, and post-route ECOs; tapeout-ready in 18 months with zero re-spins.
- Drove first-silicon bring-up for 2 SoC variants in the lab via JTAG, scan-dump, and on-chip logic analyzers, and root-caused 14 silicon bugs with 3 metal-layer ECOs.
- Translated chip and IP architecture specs into 12 detailed design specs and register maps, partnering with architects on PPA trade-offs and feature partitioning; adopted as team baseline across 4 product lines.
- Partnered with Architecture, DV, DFT, and Physical Design teams across 4 SoC product lines, authoring 20 verification-plan and DFT docs that became the team's RTL baseline and onboarding 3 new ASIC engineers into the team's design-review and bring-up workflow.