Dear AMD Talent Acquisition team,
I am writing to throw my hat in for the FPGA Engineer role listed on your careers page. FPGA engineering has been my main line of work for years, and I would be glad to carry it over to your team.
I did some homework on AMD first, and what jumped out was your adaptive SoC roadmap and the engineering talks your team keeps posting on high-speed SerDes. This strikes me as a good time to come on board, and I would be glad to steer my FPGA engineering experience toward it.
Reading through your posting, the three areas you care about most are RTL design in Verilog and SystemVerilog, timing closure and synthesis and verification with UVM testbenches. Those are what make or break an FPGA hire, and I have solid results in each.
On RTL design in Verilog and SystemVerilog, I work in Verilog, SystemVerilog and VHDL. As an FPGA Engineer at Marvell, I wrote an AXI DMA engine in SystemVerilog that sustained 12 GB/s to DDR4. Beyond that, I built the reusable IP-block library the design team now reuses.
For timing closure and synthesis, I rely on Vivado, static timing analysis and constraints. As an FPGA Engineer at Marvell, I fixed a failing 400 MHz datapath by re-pipelining it and closed timing with 0.2ns of slack.
On verification with UVM testbenches, I bring UVM, SystemVerilog assertions and code coverage. As an FPGA Engineer at Marvell, I built a UVM testbench that drove functional coverage to 98%. Beyond that, I wrote the nightly regression suite the whole team now runs.
I would be glad to take you through any of it in an interview and make the case for why I fit. I am ready to open the waveform viewer, help the team ship working silicon, and keep improving as it grows.
Thank you for reading, and I hope we can set up a time to talk.
Yours sincerely,
Theo Script
theo.script@gmail.com