FPGA Engineer Resume
Skills & ATS Keywords

Aim for 42 to 56 named items: HDLs, vendor toolchains, verification stacks, IP cores, on-chip buses, timing + CDC tools, soft-core platforms, and DSP / application standards, grouped into 7 to 8 RTL-discipline rows. Below 34 reads as a fresh-grad file that has not yet closed timing on a real build; above 62 starts looking like a vendor brochure rather than an engineer. Every chip should map back to an RTL block you signed off, a UVM testbench you closed coverage on, an STA report you brought to Fmax, an IP core you authored, or a CDC sign-off you ran.

Drop the Technical Skills block straight under the Profile Summary and ahead of the job history. FPGA hiring managers move through the file in three passes: the summary, then the HDL + toolchain + verification rows, then the RTL bullets that prove the claims. Workday, iCIMS, and Greenhouse all weight a labeled block near the top of the file more heavily than the same vocabulary buried in paragraphs. Slice the inventory into 7 to 8 named rows by RTL discipline (HDLs, Vendor Toolchains, Verification, HLS, Timing + CDC, IP Cores + Interconnect, Soft-Core + SoC, DSP + Standards) rather than one undifferentiated comma string.

Lift 16 to 22 of the most repeated nouns out of the requisition: the HDL set (Verilog, SystemVerilog, VHDL), the vendor tool (Vivado, Vitis HLS, Quartus, Libero), the verification stack (UVM, JasperGold, SpyGlass CDC), the IP and bus list (AXI4, PCIe Gen 5, DDR5, 100GbE), the SoC platform (Zynq UltraScale+, Versal, Agilex SoC), and the application or standards tag (5G NR L1, DO-254, ISO 26262). Plant every term into the Skills row AND into the bullet that backs it. Then push the file through an ATS Checker so you can see exactly what the parser picked up.

An Embedded Software Engineer resume reads as firmware on the MCU or SoC: bare-metal C, RTOS, drivers, ISRs, board bring-up from the software side. An ASIC Engineer resume reads as full silicon design through tape-out: physical implementation, DFT + scan + ATPG, library characterization, foundry sign-off, mask costs the size of a small house. An FPGA Engineer resume sits in between on purpose: the same RTL vocabulary (Verilog, SystemVerilog, UVM, STA, CDC) and the same IP set (AXI4, DDR, PCIe, Ethernet) as the ASIC file, but the silicon is programmable, the build cycle is hours rather than months, and the deliverable is a bitstream on a Xilinx UltraScale+, an Intel Agilex, a Lattice CertusPro, or a Microchip PolarFire instead of a taped-out die. If the file shows firmware drivers and RTOS, you read as Embedded; if it shows place + route on a 5 nm node, DRC + LVS clean, and a foundry hand-off, you read as ASIC; if it shows Vivado timing reports closed at Fmax, UVM coverage closure, AXI4 IP cores authored, and a Zynq or Agilex SoC integration, you read as FPGA.

Read the requisition first. Defense + aerospace + medical FPGA roles in the US still skew VHDL-first, especially anything DO-254 or ISO 26262 adjacent. Commercial datacenter, networking, HFT, and consumer roles run SystemVerilog for RTL and UVM for verification, with Verilog as the lower common denominator. If the JD names SystemVerilog, lead with it on the HDL row and back it up with UVM, SVA assertions, classes, and constrained-random in the Verification row. If the JD names VHDL, lead VHDL and pair it with a verification stack the panel will recognize (OSVVM, UVVM, or a SystemVerilog + UVM cross-train if you have it). Naming all three with no signal of where your real depth sits reads as a tourist.

At junior and mid, no: a strong UVM + constrained-random testbench, functional coverage closure, and clean STA reports are enough to pass the screen. At senior and staff in 2026, formal (JasperGold, Synopsys VC Formal, OneSpin) starts showing up on roughly a third of US FPGA postings, mostly for cache coherency, FIFO depth proofs, register-map sweeps, and CDC sign-off. HLS (Vitis HLS, Intel HLS Compiler, Catapult, Stratus) appears on closer to two-thirds at staff, especially for DSP and ML acceleration. If you have a property set you wrote in SVA or PSL, name it; if you have a C++ kernel that compiled to RTL and met Fmax, name that too. If you do not have either, lead harder on UVM, STA closure, and AXI / PCIe IP integration so the senior shape is unmistakable elsewhere on the page.

Six metric families carry an FPGA file. Timing closure (target Fmax in MHz, WNS / TNS slack after place + route, multi-cycle and false-path counts cleaned). Resource use (LUT, FF, BRAM, URAM, DSP48 utilization percent on the target device). Verification depth (functional coverage percent closed, code coverage percent, UVM testbench seed count, assertion count). Throughput + latency (Gbps on the SerDes lane, packets per second through the datapath, end-to-end latency in ns or cycles on a critical path). Power + thermal (static + dynamic power in W from Vivado Power Analyzer or Intel PowerPlay, junction-temp headroom). Regulatory closure (DO-254 DAL level, ISO 26262 ASIL grade, DO-178C cross-discipline trace). Pair each one with the tool, the device, or the standard that produced it so both the chief FPGA engineer and the parser pick the proof up.