Dear Qualcomm Talent Acquisition team,
I want to put myself forward for the ASIC Engineer role you have posted on your careers page. ASIC engineering has been the core of my work for a long time, and I would be glad to put it to work for you.
I looked into Qualcomm ahead of writing, and what stuck with me was your custom silicon program and the deep-dive talks your engineers keep posting on low-power design. It seems like a fine moment to join, and I would gladly bring my ASIC engineering experience to bear on it.
Looking over the posting, the three areas you value most are RTL-to-GDSII synthesis and physical design, static timing analysis and sign-off and design for test and low-power flows. Those decide whether an ASIC hire works out, and I can point to hard results in each.
On RTL-to-GDSII synthesis and physical design, I work with Synopsys Design Compiler, ICC2 and Fusion Compiler. As an ASIC Engineer at Broadcom, I drove a compute block from RTL to GDSII and closed it at 7nm with clean sign-off. Beyond that, I built the reusable timing-constraint decks the physical-design team now starts from.
For static timing analysis and sign-off, I depend on PrimeTime, multi-corner sign-off and CTS. As an ASIC Engineer at Broadcom, I resolved a multi-corner timing violation spread across 200 paths by re-floorplanning it and pulled back 15% of the area.
On design for test and low-power flows, I bring DFT scan insertion, UPF and power gating. As an ASIC Engineer at Broadcom, I ran scan insertion that reached 99% stuck-at coverage. Beyond that, I wrote the UPF power-intent flow the whole team standardized on.
I would happily walk you through any of this in an interview and lay out why I fit. I am ready to dig into the flow, help the team push clean silicon out the door, and keep growing with it.
Thanks for your time reading this, and I hope we can talk soon.
Yours sincerely,
Theo Script
theo.script@gmail.com